Greenleaf Software Reference Library: UART Devices: List & Explanation

Model	FIFO Depth (bytes)	Max Kbps	Made by	DataSheet PDF	Notes
8250	0	19.2	National
82C50A	0	625	Harris
PC16550D	16	128	National
NS16C552	16	128	National		Dual UART
TL16C450	0	50	Texas InStr
TL16C550	16	1000	Texas Instr		Autoflow modes
TL16C750	64	1000	Texas InStr		Autoflow modes
TL16PC564A	64	115.2	Texas InStr		AutoFlow, PCMCIA Interface
ST16C650	32	460.8	Startech (Exar)
OX16C954	128	50,000	Oxford		Quad UART
OX16C950 Rev B	128	15,000	Oxford		Programmable 450…950
OX16C954B	128	60,000	Oxford		Quad, Multi-mode (incl. 650,750,850)

About UART FIFOs and Greenleaf ViewComm Async II	What is a UART? In the late 1970s, UARTs (Universal Asynchronous Receiver Transmitter) devices began to reach the stage of single chip logic, and when the IBM PC arrived in the early 80s, it encompassed two 8250 UART chips which provided for COM1 and COM2. The task of a UART is to convert parallel (8 bit bytes) from memory to a coherent serial stream of bits at the transmitter and do the reverse at the receiver. Add to that the ability for each of a communicating pair of UARTs to both transmit and receive simultaneously and you have a modern full-duplex link. “coherent serial stream of bits” means adding some control bits to maintain the ability of the receiver to discern the beginning of a symbol and its end, and to add the optional ability to detect single bit errors in a symbol (character, byte, etc.)

	The Humble 8250 UART The humble 8250 ran at speeds up to 19,200 baud, had no FIFOs, and many years later, the same basic logic is supporting far faster baud rates.

	What is a FIFO? FIFO buffers have been added to reduce processor interrupt rates, and numerous additional goodies like automatic flow control have evolved. Today, you can get as many serial ports in a PCMCIA card as you can finagle pins on the edge to connect to the world.

	What good is a FIFO anyway? Focus now, if you will, on the FIFO buffers in today’s typical UART. What purpose do they serve (other than allegecly reducing processor interrupt rates)? The truth is: not much. Arguments for and against a FIFO buffer On the input (receive) side, you could lose data if the processor isn’t available to remove data from the receive stream. That would be a receiver overrun and it is an error. But if you add bytes to the depth of the FIFO, you reach a point where it is not pragmatic to add more. Or the manufacturing engineers tell you that you must give up functionality here or elsewhere (in order to keep cost down and profit up).

	What does a UART look like to software? At a fundamental level, all forms of UART used in Windows machines and the like are essentially a group of about logical registers, each one octet (byte if you prefer) in width addressable in I/O space. Physically, there are 8 registers but some are shadowed read / write, meaning the effective address of a particular register has a different meaning when accessed for write than for read operations. As an example, physical register 0 is implemented as 8 read-only bits (Receiver Buffer Register) and, at the same I/O address, 8 write-only bits (Transmitter Holding Register). Each of the UART DataSheets listed in this section contains a “map” of the accessible registers.

	Enter ViewComm, Stage Left Now, along comes ViewComm. The magic of ViewComm Async is that it can “see” everything the UART “knows” at each time the UART requests a hardware interrupt. There are four reasons that a UART will raise an IRQ (interrupt request): Receiver buffer full, processor must Empty Transmitter buffer Empty, processor must feed Modem status change Line status change

	ViewComm needs to see “Everything” every time any one or more of these events occurs. This is done by the replacement of the standard Microsoft Windows serial driver with a special driver that replaces the software logic that gets executed when any hardware interrupt occurs on a port–the Interruptand Service Routine (ISR) is executed. (Don’t confuse this ISR with the Interrupt Status Register, which is a hardware register in some UARTs that holds status of the FIFO.

	instead of attending only to the functionality represented by the reason for the IRQ, the ViewComm driver attends to ALL of the functions. If a received character is available, the driver grabs it; if there’s an empty transmit buffer (or FIFO), the driver asks the processor to transfer enough data to fill the transmitter pipeline. Modem and Line status bytes are grabbed, and a 64-bit timestamp is appended to the information transferred.

	In this manner, we can be assured that every time anything that can ask the CPU for help (an IRQ is raised), everything is kept synchronized as closely in time as possible; the UART can, in fact, reach a full Receive buffer and an Empty transmit buffer, several kinds of errors, and some modem control or status lines may change–all at once.

How Wide is the FIFO?	Some UART devices have 11 bit wide FIFOs, so that you can store 8 data bits plus some status bits for each position in the FIFO. This argues against using “no FIFO” which is the way ViewComm worked a few years ago. But “no FIFO” (which means a depth of 1 including the receive data register) means more interrupts per unit time together with more processing done each UART interrupt, so in a sense, the situation becomes worse, not better. The strategy (using FIFOs) of reducing interrupts per unit time has boomeranged and the hoped for improvement is further counteracted by the loss of information stored with each interrupt occurence.

	Er…Loss of information… Yes. Altogether we hope to store 8 Tx bits, 8 Rx bits, from 12 to 16 bits of status, and 64-bit timestamp: a total of 96 bits. Instead, we lose the timestamp altogether (see below) and FIFO width is barely enough for manufacturers to be able to say they are storing “status” along with each character in or out. Of course, with 3 status bits, the implication is clear: When a received character is pushed into the receive FIFO along with 3 bits of status, these bits are different from the ones stored in the transmit FIFO.

Notes about Baud Rate	What is a baud? First, what a baud isn’t. It is not a code. Ah, but Baudot IS a code. Confused yet? In 1870, Emile Baudot invented a 5-bit “folded” code for telegraphy. By “folded” I mean one “escape” code was reserved to switch between alphabetic and numeric / special characters. Greenleaf ViewComm II can interpret Baudot code set. For efficiency, it is usually sent at 5 data bits and 1 1/2 stop bits. Baud rate is an often ill-understood term, mistaken to mean number of characters per second. That is false. Baud rate means bits per second. 115 Kbaud means 115,000 bits per second, or as it is usually expressed, 115 Kbps.

	A good deal of async communications takes place at 8 bits per character (word length), no parity, 1 stop bit. To this you add one start bit and you end up with ten bits per character on the line. Although asynchronous truly means you can have an indeterminate / unspecified delay (space) between adjacent characters on the line, there is rarely a need for such space and so we can speak of actual data rate as being the same as baud rate divided by total bits per character. Note–often a “character” is called a symbol.

	In (all or very Close to all) UARTs, two 8-bit registers are linked together logically to form one 16-bit divisor. This divisor is written to the registers and is used to divide into the clock rate to get baud rate. Baud rate * divisor = clock rate. There is no logical restriction or rule about what 16-bit number you can use as divisor.

	For pragmatic reasons, certain baud rates became “standard” or “accepted” in the industry. As an example, an early UART that is in use in a great many computers today is the T.I. 16550C (revision C). An urban myth is that the upper limit of baud rate for the 16550 on your laptop is 115,200. Actually, whatever else, the baud rate * 16 is the required internal clock frequency (16 clocks per bit). The T.I. datasheet for the 16550C indicates a nominal clock rate of 1.8432 Mhz. If you divide this by 16 you get 115,200. Since the clock is divided internally by 16 in addition to being divided by the content of the divisor in the aforementioned registers, the divisor would be 1 to attain 115.2 Kbps.

	Another erstwhile myth is that you can “only get” the standard set of baud rates, e.g. 300,600,1200,…56000,115200. Earlier we noted that the divisor can be anything. Let’s say we want to use 48,216 baud. Divide 18432 / 48216 = 382279.7 then divide again by 16, we get 23892. The question now is: How close is this to a binary number represented by 16 bits? Try Hex 5d54 — that’s exact, and all you have to do is give up the silly idea about multiples of 600 or whatever.

	Another way (it depends upon how much you want to spend) is to use an external clock and adjust the frequency so that it is an exact multiple of 48216. To do your math for you, a clock at 6.17165 Mhz divided by 16 and then the baud rate gives you a divisor of 8. There are other combinations, and the point is that Greenleaf ViewComm uses Windows ComboBox elements for baud rate selection–meaning you can type in your desired rate (and the system will get as close as possible given the a-priori rule that the divisor nust be a 16-bit binary number. We’ve noted this twice so may as well say it: You could get better accuracy, get closer to your desired baud rate if you could use a larger divisor (say 24 or 32 bits).

	The actual numbers you will have to work with are dependent upon the clock frequency. Check with the manufacturer of add-on cards to find out the clock frequency. Or just experiment. But know that there are few absolutes in serial communications. And that you can work out “non-standard” baud rates in at least two manners.

Summarizing…and what’s up next?	The revision C 16550 UART can run at up to 1 Mbps, so there goes another myth. Thing is, nobody needs it to drive a modem anymore and you have to really watch the cable length. There is a tradeoff that is not a myth except in the negative sense that not everyone seems to recognize it. This is why systems running around factory floors amongst arc welders and giant grinders use RS-485 or RS-422. This is food for another day and another topic in our Reference section, but very briefly, balanced line drivers / receivers are excellent at what they do which is significantly reduce common mode noise so that signals can travel longer distance and Function. You usually have to run lower baud rates but you gain versatility (arc welders yesss!) and reliability.